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w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 1 - revision a 01 - 00 3 table of contents 1. general descripti on ................................ ................................ ................................ .......... 4 2. features ................................ ................................ ................................ ................................ .. 4 3. pin configuration ................................ ................................ ................................ ................ 5 3.1 ball assignment: lpddr x16 ................................ ................................ ................................ .......... 5 3.2 ball assignment: lpddr x32 ................................ ................................ ................................ .......... 5 4. pin description ................................ ................................ ................................ ..................... 6 4.1 signal descriptions ................................ ................................ ................................ ........................... 6 4.2 addressing table ................................ ................................ ................................ ............................. 7 5. block diagram ................................ ................................ ................................ ...................... 8 5.1 block diagram ................................ ................................ ................................ ................................ .. 8 5.2 simplified s tate diagram ................................ ................................ ................................ .................. 9 6. function descript ion ................................ ................................ ................................ ....... 10 6.1 initialization ................................ ................................ ................................ ................................ .... 10 6.1.1 initialization flow diagram ................................ ................................ ................................ .................... 11 6.1.2 initialization waveform sequence ................................ ................................ ................................ ......... 12 6.2 register definition ................................ ................................ ................................ .......................... 12 6.2.1 mode register set operation ................................ ................................ ................................ ................ 12 6.2.2 mode register definition ................................ ................................ ................................ ....................... 13 6.2.3. burst length ................................ ................................ ................................ ................................ ......... 13 6.3 burst definition ................................ ................................ ................................ ............................... 14 6.4 burst ty pe ................................ ................................ ................................ ................................ ...... 15 6.5 read latency ................................ ................................ ................................ ................................ . 15 6.6 extended mode register description ................................ ................................ ............................. 15 6.6.1 extended mode register definition ................................ ................................ ................................ ...... 16 6.7 status register read ................................ ................................ ................................ ..................... 16 6.7.1 srr register (a[n:0] = 0) ................................ ................................ ................................ ..................... 17 6.7.2 status register read timing diagram ................................ ................................ ................................ . 18 6.8 partial array self refresh ................................ ................................ ................................ ............... 19 6.9 automatic temperature compensated self refresh ................................ ................................ ....... 19 6.10 output drive strength ................................ ................................ ................................ ................... 19 6.11 commands ................................ ................................ ................................ ................................ ... 19 6.11.1 basic timing parameters for commands ................................ ................................ ........................... 19 6.11.2 truth table - commands ................................ ................................ ................................ .................... 20 6. 11.3 truth table - dm operations ................................ ................................ ................................ .............. 21 6.11.4 truth table - cke ................................ ................................ ................................ ............................... 21 6.11.5 truth table - current state bankn - command to bankn ................................ ............................... 22 6.11.6 truth table - current state bankn, command to bankn ................................ ................................ . 23 7. operation ................................ ................................ ................................ .............................. 24 7.1. deselect ................................ ................................ ................................ ................................ ........ 24 7.2. no operation ................................ ................................ ................................ ................................ . 24 7.2.1 nop command ................................ ................................ ................................ ................................ ..... 25
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 2 - revision a 01 - 00 3 7.3 mode register set ................................ ................................ ................................ .......................... 25 7.3.1 mode register set command ................................ ................................ ................................ ............... 25 7.3.2 mode register set command timing ................................ ................................ ................................ ... 26 7.4. active ................................ ................................ ................................ ................................ ............ 26 7.4.1 active command ................................ ................................ ................................ ................................ ... 26 7.4.2 bank activation command cycle ................................ ................................ ................................ .......... 27 7.5. read ................................ ................................ ................................ ................................ ............. 27 7.5.1 read command ................................ ................................ ................................ ................................ .... 28 7.5.2 basic read timing parameters ................................ ................................ ................................ ............ 28 7.5.3 read burst showing cas latency ................................ ................................ ................................ ....... 29 7.5.4 read to read ................................ ................................ ................................ ................................ ........ 29 7.5. 5 consecutive read bursts ................................ ................................ ................................ ...................... 30 7.5. 6 non - consecutive read bursts ................................ ................................ ................................ .............. 30 7.5. 7 random read bursts ................................ ................................ ................................ ............................ 31 7.5. 8 re ad burst terminate ................................ ................................ ................................ ........................... 31 7.5. 9 read to write ................................ ................................ ................................ ................................ ........ 32 7.5. 10 read to pre - charge ................................ ................................ ................................ ............................. 32 7.5.11 burst terminate of read ................................ ................................ ................................ ..................... 33 7.6 write ................................ ................................ ................................ ................................ ............... 33 7.6.1 write command ................................ ................................ ................................ ................................ .... 34 7.6.2 basic write timing parameters ................................ ................................ ................................ ............. 34 7.6.3 write burst (min. and max. tdqss) ................................ ................................ ................................ ...... 35 7.6.4 write to write ................................ ................................ ................................ ................................ ......... 35 7.6.5 concat enated write bursts ................................ ................................ ................................ ................... 36 7.6.6 non - consecutive write bursts ................................ ................................ ................................ .............. 36 7.6.7 random write cycles ................................ ................................ ................................ ........................... 37 7.6.8 write to read ................................ ................................ ................................ ................................ ........ 37 7.6.9 non - in terrupting write to read ................................ ................................ ................................ ............. 37 7.6.10 interrupting write to read ................................ ................................ ................................ ................... 38 7.6.11 write to precharge ................................ ................................ ................................ .............................. 38 7.6.12 non - interrupting write to precharge ................................ ................................ ................................ ... 38 7.6.13 interrupting write to precharge ................................ ................................ ................................ ........... 39 7.7 precharge ................................ ................................ ................................ ................................ ....... 39 7.7.1 precharge command ................................ ................................ ................................ ............................ 40 7.8 auto precharge ................................ ................................ ................................ .............................. 40 7.9 refresh requirements ................................ ................................ ................................ .................... 40 7.10 auto refresh ................................ ................................ ................................ ................................ 40 7.10.1 auto re fresh command ................................ ................................ ................................ ...................... 41 7.11 self referesh ................................ ................................ ................................ ................................ 41 7.11.1 self refresh command ................................ ................................ ................................ ....................... 42 7.11.2 auto refresh cycles back - to - back ................................ ................................ ................................ ..... 42 7.11.3 self refresh entry and exit ................................ ................................ ................................ ................. 43 7.12 power down ................................ ................................ ................................ ................................ . 43 7.12.1 power - down entry and exit ................................ ................................ ................................ ................ 43 7.13 deep power down ................................ ................................ ................................ ........................ 44
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 3 - revision a 01 - 00 3 7.13.1 deep power - down entry and exit ................................ ................................ ................................ ....... 44 7.14 clock stop ................................ ................................ ................................ ................................ .... 45 7.14.1 clock sto p mode entry and exit ................................ ................................ ................................ ......... 45 8. electrical charac teristic ................................ ................................ ........................... 46 8.1 absolute maximum ratings ................................ ................................ ................................ ............ 46 8.2 input/output capacitance ................................ ................................ ................................ ............... 4 6 8.3 electrical characteristics and ac/dc operating conditions ................................ ........................... 47 8.3.1 electrical characteristics and ac/dc operating conditions ................................ ................................ 47 8.4 idd specification parameters and test conditions ................................ ................................ ........ 48 8.4.1 idd specification parameters and test conditions ................................ ................................ .............. 48 8.5 ac timings ................................ ................................ ................................ ................................ ..... 51 8.5.1 cas latency definition (with cl=3) ................................ ................................ ................................ ..... 54 8.5.2 output slew rate characteristics ................................ ................................ ................................ ......... 55 8.5.3 ac overshoot/undershoot specification ................................ ................................ .............................. 55 8.5.4 ac overshoot and undershoot definition ................................ ................................ ............................. 55 9. package dimension s ................................ ................................ ................................ ......... 56 9.1: lpddr x 16 ................................ ................................ ................................ ................................ .. 56 9.2: lpddr x 32 ................................ ................................ ................................ ................................ .. 57 10. ordering informa tion ................................ ................................ ................................ ... 58 11. revision history ................................ ................................ ................................ ............... 59
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 4 - revision a 01 - 00 3 1. general description w 94 7 d6 h b / w 94 7 d2 h b is a high - speed low power double data rate synchronous dynamic random access memory ( lp ddr sdram), an access to the lp ddr sdram is burst oriented. consecutive memory location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an active command. column addresses are automatically generated by the lp ddr sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the pre - charging time. by setting programmable mode register s , the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. the device supports speci al low power functions such as partial array self refresh (pasr) and automatic temperature compensated self refresh (atcsr). 2 . features vdd = 1. 7~1.95 v vddq = 1. 7~1.95 v ; data width: x16 / x32 clock rate: 200mhz( - 5), 166mhz ( - 6) ,1 33 mhz ( - 75) partial array self - refresh(pasr) auto temperature compensated self - refresh(atcsr) power down mode deep power down mode (dpd mode) programmable output buffer driver strength four internal banks for concurrent operation data mask (dm) for write data clock stop capability during idle periods auto pre - charge option for each burst access double data rate for data output differential clock inputs (ck and ) bidirectional, data strobe (dqs) latency: 2 and 3 burst length: 2, 4, 8 and 16 burst type: sequential or interleave 64 ms refresh period interface: lvcmos compatible support package: 60 balls bga (x16) 90 balls bga (x32) operating temperature range : extended ( - 25 c ~ +85 c) industrial ( - 40 c ~ + 85 c) ck cas
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 5 - revision a 01 - 00 3 3 . pin configuration 3 .1 ball assignment: lpddr x16 60 ball vfbga 1 2 3 4 5 6 7 8 9 a vss dq15 vssq vddq dq0 vdd b vddq dq13 dq14 dq1 dq2 vssq c vssq dq11 dq12 dq3 dq4 vddq d vddq dq9 dq10 dq5 dq6 vssq e vssq udqs dq8 dq7 ldqs vddq f vss udm nc nc ldm vdd g cke ck h a9 a11 nc ba0 ba1 j a6 a7 a8 a10/ap a0 a1 k vss a4 a5 a2 a3 vdd (top view) pin configuration 3 .2 ball assignment: lpddr x32 90 ball vf bga 1 2 3 4 5 6 7 8 9 a vss dq31 vssq vddq dq16 vdd b vddq dq29 dq30 dq17 dq18 vssq c vssq dq27 dq28 dq19 dq20 vddq d vddq dq25 dq26 dq21 dq22 vssq e vssq dqs3 dq24 dq23 dqs2 vddq f vdd dm3 nc nc dm2 vss g cke ck h a9 a11 nc ba0 ba1 j a6 a7 a8 a10/ap a0 a1 k a4 dm1 a5 a2 dm0 a3 l vssq dqs1 dq8 dq7 dqs0 vddq m vddq dq9 dq10 dq5 dq6 vssq n vssq dq11 dq12 dq3 dq4 vddq p vddq dq13 dq14 dq1 dq2 vssq r vss dq15 vssq vddq dq0 vdd (top view) pin configuration ck we cas ras cs
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 6 - revision a 01 - 00 3 4 . pin description 4.1 signal descriptions signal name type function description a [n : 0] input address provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. the address inputs also provide the opcode during a mode register set command. a10 is used for auto pre - charge select . ba0, ba1 input bank select define to which bank an active, read, write or precharge command is being applied. dq0~dq15 (16) dq0~dq31 (32) i/o data input/ output data bus: input / output. input chip select enables (registered low) and disables (registered high) the command decoder. all commands are masked when is registered high. provides for external bank selection on systems with multiple banks. is considered part of the command code. input row address strobe , and (along with ) define the command being entered. input column address strobe referred to input write enable referred to udm / ldm(x16) ; dm0 to dm3 (x32) input input mask input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input - only, the dm loading matches the dq and dqs loading. x16: ldm: dq0 - dq7, udm: dq8 C dq15 x32 : dm0: dq0 - dq7, dm1: dq8 C dq15, dm2: dq16 C dq23, dm3: dq24 C dq31 ck / input clock inputs ck and are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of . input and output data is referenced to the crossing of ck and (both directions of crossing). internal clock signals are derived from ck/ . ck we cas ras cs ras
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 7 - revision a 01 - 00 3 signal name type function description cke input clock enable cke high activates, and cke low deactivates internal clock signals, and device input buffers and out put drivers. taking cke low provides precharge, power down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. inpu t buffers, excluding ck, and cke, are disabled during power down and self refresh mode which are contrived for low standby power consumption. ldqs, udqs (x16); dqs0~dqs3 (x32) i/o data s trobe output with read data, input with write data. edge - aligned with read data, centered with write data. used to capture write data. x16: ldqs: dq0~dq7; udqs: dq8~dq15. x32: dqs0: dq0~dq7; dqs1: dq8~dq15; dqs2: dq16~dq23; dqs3: dq24~dq31. vdd supply power power supply for input buffers and internal circuit. vss supply ground ground for input buffers and internal circuit . vddq supply power for i/o buffer power supply separated from vdd, used for output drivers to improve noise. vssq supply ground for i/o buffer ground for output drivers. nc - no connect non connection pin . 4.2 addressing table item 128mb number of banks 4 bank address pins ba0,ba1 auto precha r ge pin a10 /ap x 16 row addresses a0 - a1 1 column addresses a0 - a 8 trefi (s) 15.6 x32 row addresses a0 - a1 1 column addresses a0 - a 7 trefi (s) 15.6 ck
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 8 - revision a 01 - 00 3 5 . block diagram 5.1 block diagram u d m / l d m ( x 1 6 ) c k c k e c s r a s c a s w e a 1 0 a 0 a n b a 0 b a 1 c l o c k b u f f e r c o m m a n d d e c o d e r a d d r e s s b u f f e r r e f r e s h c o u n t e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r m o d e r e g i s t e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 2 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 0 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 3 d a t a c o n t r o l c i r c u i t d q b u f f e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 1 d m n r o w d e c o r d e r r o w d e c o r d e r r o w d e c o r d e r r o w d e c o r d e r d q 0 C d q 1 5 ( x 1 6 ) d q 0 C d q 3 1 ( x 3 2 ) d m n ( x 3 2 ) u d q s / l d q s ( x 1 6 ) d q s n ( x 3 2 ) c k
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 9 - revision a 01 - 00 3 5.2 simplified state diagram a c t = a c t i v e m r s = e x t . m o d e r e g . s e t r e f s x = e x i t s e l f r e f r e s h b s t = b u r s t t e r m i n a t e m r s = m o d e r e g i s t e r s e t r e a d = r e a d w / o a u t o p r e c h a r g e c k e l = e n t e r p o w e r - d o w n p r e = p r e c h a r g e r e a d a = r e a d w i t h a u t o p r e c h a r g e c k e h = e x i t p o w e r - d o w n p r e a l l = p r e c h a r g e a l l b a n k w r i t e = w r i t e w / o a u t o p r e c h a r g e d p d s = e n t e r d e e p p o w e r - d o w n r e f a = a u t o r e f r e s h w r i t e a = w r i t e w i t h a u t o p r e c h a r g e d p d s x = e x i t d e e p p o w e r - d o w n r e f s = e n t e r s e l f r e f r e s h n o t e : u s e c a u t i o n w i t h t h i s d i a g r a m . i t i s i n d e n t e d t o p r o v i d e a f l o o r p l a n o f t h e p o s s i b l e s t a t e t r a n s i t i o n s a n d c o m m a n d s t o c o n t r o l t h e m , n o t a l l d e t a i l s . i n p a r t i c u l a r s i t u a t i o n s i n v o l v i n g m o r e t h a n o n e b a n k a r e n o t c a p t u r e d i n f u l l d e t a l l . d e e p p o w e r d o w n d p d s a c t p r e p r e p r e r e a d a r e a d a p r e c h a r g e p r e a l l w r i t e a p r e w r i t e r e a d b u r s t s t o p r o w a c t i v e a c t i v e p o w e r d o w n p r e c h a r g e p o w e r d o w n a u t o r e f r e s h i d l e a l l b a n k s p r e c h a r g e d m r s e m r s s e l f r e f r e s h p r e c h a r g e a l l b a n k p o w e r o n p o w e r a p p l i e d d p d s x m r s r e f a r e f s r e f s x c k e l c k e h c k e h c k e l w r i t e w r i t e a r e a d a b s t r e a d r e a d a r e a d w r i t e r e a d w r i t e a u t o m a t i c s e q u e n c e c o m m a n d s e q u e n c e s r r r e a d r e a d s r r s r r = s t a t u s r e g i s t e r r e a d
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 10 - revision a 01 - 00 3 6 . f unction description 6 .1 i niti alization lpddr sdram must be powered up and initialized in a predefined manner. operations procedures other than those specified may result in undefined operation. if there is any interruption to the device power, the initialization routine should be followed. the steps to be followed for device initialization are listed below. the m ode r egister and e xtended m ode r egister do not have default values. if they are not programmed during the initialization sequence, it may lead to unspecified operation. the clock stop feature is not a v ailable until the device has b een properly initialized from step 1 through 11. ? step 1: provide power, the device core power (vdd) and the device i/o power (vddq) must be brought up simultaneously to prevent device latch - up. although not required, it is recommended that vdd and vddq are from the same power source. also assert and hold clock enable (cke) to a lvcmos logic high level ? step 2: once the system has established consistent device power and cke is driven high, it is safe to apply stable clock. ? step 3: there must be at least 200 s of valid clocks before any command may be given to the dram. during this time nop or deselect commands must be issued on the command bus. ? step 4: issue a precharge all command. ? step 5: provide nops or deselect commands for at least trp time. ? step 6: issue an auto refresh command followed by nops or deselect command for at least trfc time. issue the second auto refresh command followed by nops or deselect command for at least trfc time. note as part of the initialization sequence there must be two auto refr esh commands issued. the typical flow is to issue them at step 6, but they may also be issued between steps 10 and 11. ? step 7: using the mr s command, program the base mode register. set the desired operation modes. ? step 8: provide nops or deselect commands for at least tmrd time. ? step 9: using the mr s command, program the extended mode register for the desired operating modes. note the order of the base and extended mode register programmed is not important. ? step 10: provide nop or deselect commands for at least tmrd time. ? step 11: t he dram has been properly initialized and is ready for any valid command.
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 11 - revision a 01 - 00 3 6.1.1 initialization flow diagram 1 v d d a n d v d d q r a m p : c k e m u s t b e h e l d h i g h 2 a p p l y s t a b l e c l o c k s 3 w a i t a t l e a s t 2 0 0 u s w i t h n o p o r d e s e l e c t o n c o m m a n d b u s 4 p r e c h a r g e a l l 5 a s s e r t n o p o r d e s e l c t f o r t r p t i m e 6 i s s u e t w o a u t o r e f r e s h c o m m a n d s e a c h f o l l o w e d b y n o p o r d e s e l e c t c o m m a n d s f o r t r f c t i m e 7 c o n f i g u r e m o d e r e g i s t e r 8 a s s e r t n o p o r d e s e l e c t f o r t m r d t i m e 9 c o n f i g u r e e x t e n d e d m o d e r e g i s t e r 1 0 a s s e r t n o p o r d e s e l e c t f o r t m r d t i m e 1 1 l p d d r s d r a m i s r e a d y f o r a n y v a l i d c o m m a n d
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 12 - revision a 01 - 00 3 6.1.2 initialization waveform sequence 6 . 2 r egister d efinition 6 .2.1 m ode r egister s et o peration the mode register is used to define the specific mode of operation of the lpddr sdram. this definition includes the definition of a burst length, a burst type, a cas latency as shown in the following figure. the mode register is programmed via the mode register set command (with ba0=0 and ba1=0) and will retain the stored information until it is reprogrammed, the device goes into deep power down mode, or the device loses power. mode register bits a0 - a2 specify the burst length, a3 the type of b urst (sequential or interleave), a4 - a6 the cas latency. a logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. the mode register must be loaded when all banks are idle and no bursts are in progress, and the contr oller must wait the specified time tmrd before initiating any subsequent operation. violating either of these requirements will result in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future version s may result. v d d v d d q c k c k c k e c o m m a n d a d d r e s s a 1 0 b a 0 , b a 1 d m d q , d q s 2 0 0 u s t c k t r p t r f c t r f c t m r d t m r d n o p p r e a r f a r f m r s m r s a c t c o d e c o d e c o d e c o d e r a r a b a b a 0 = l b a 1 = l b a 0 = l b a 1 = h a l l b a n k s ( h i g h - z ) v d d / v d d q p o w e r e d u p c l o c k s t a b l e l o a d m o d e r e g . l o a d e x t . m o d e r e g . . = d o n ' t c a r e
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 13 - revision a 01 - 00 3 6.2.2 mode register definition 6 .2. 3 . b urst l ength read and write accesses to the lpddr sdram are burst oriented, with the burst length and burst type being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. when a read or write co mmand is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within the bloc k , meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a 1 ? an when the burst length is set to two, by a2 ? an when the burst length is set to 4, by a3 ? an when the burst length is set to 8 (where an is the most significant column address bit for a given configuration). the remaining (least significant) address bit( s) is (are) used to select th e starting location within the b lock. the programmed burst length applies to both read and write bursts. a 6 a 5 a 4 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 c a s l a t e n c y r e s e r v e d a 2 a 1 a 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 b u r s t l e n g t h r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d 2 4 8 1 6 r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d 2 3 a 3 0 1 b u r s t t y p e s e q u e n t i a l i n t e r l e a v e m o d e r e g i s t e r a d d r e s s b u s a 0 a 1 a 2 a 3 a 4 a 5 a 6 a i . . a 7 ( s e e n o t e 1 ) b a 0 b a 1 0 0 0 ( s e e n o t e 2 ) c a s l a t e n c y b t b u r s t l e n g t h n o t e : 1 . m s b d e p e n d s o n l p d d r s d r a m d e n s i t y . 2 . a l o g i c 0 s h o u l d b e p r o g r a m m e d t o a l l u n u s e d / u n d e f i n e d a d d r e s s b i t s t o f u t u r e c o m p a t i b i l i t y .
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 14 - revision a 01 - 00 3 6.3 burst definition burst length starting column address order of accesses within a burst (hexadecimal notation) a3 a2 a1 a0 sequential interleaved 2 0 0 C 1 0 C 1 1 1 C 0 1 C 0 4 0 0 0 C 1 C 2 C 3 0 C 1 C 2 C 3 0 1 1 C 2 C 3 C 0 1 C 0 C 3 C 2 1 0 2 C 3 C 0 C 1 2 C 3 C 0 C 1 1 1 3 C 0 C 1 C 2 3 C 2 C 1 C 0 8 0 0 0 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 0 1 1 C 2 C 3 C 4 C 5 C 6 C 7 C 0 1 C 0 C 3 C 2 C 5 C 4 C 7 C 6 0 1 0 2 C 3 C 4 C 5 C 6 C 7 C 0 C 1 2 C 3 C 0 C 1 C 6 C 7 C 4 C 5 0 1 1 3 C 4 C 5 C 6 C 7 C 0 C 1 C 2 3 C 2 C 1 C 0 C 7 C 6 C 5 C 4 1 0 0 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 1 0 1 5 C 6 C 7 C 0 C 1 C 2 C 3 C 4 5 C 4 C 7 C 6 C 1 C 0 C 3 C 2 1 1 0 6 C 7 C 0 C 1 C 2 C 3 C 4 C 5 6 C 7 C 4 C 5 C 2 C 3 C 0 C 1 1 1 1 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 16 0 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f 0 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 - 9 - 8 - b - a - d - c - f - e 0 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 - a - b - 8 - 9 - e - f - c - d 0 0 1 1 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 - b - a - 9 - 8 - f - e - d - c 0 1 0 0 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 - c - d - e - f - 8 - 9 - a - b 0 1 0 1 5 - 6 - 7 - 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 - d - c - f - e - 9 - 8 - b - a 0 1 1 0 6 - 7 - 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 - e - f - c - d - a - b - 8 - 9 0 1 1 1 7 - 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - f - e - d - c - b - a - 9 - 8 1 0 0 0 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 8 - 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 1 0 0 1 9 - a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 9 - 8 - b - a - d - c - f - e - 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 1 0 1 0 a - b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 a - b - 8 - 9 - e - f - c - d - 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 1 0 1 1 b - c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a b - a - 9 - 8 - f - e - d - c - 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 1 0 0 c - d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b c - d - e - f - 8 - 9 - a - b - 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 1 0 1 d - e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c d - c - f - e - 9 - 8 - b - a - 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 1 0 e - f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d e - f - c - d - a - b - 8 - 9 - 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 1 f - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - a - b - c - d - e f - e - d - c - b - a - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 15 - revision a 01 - 00 3 notes: 1 . for a burst length of two, a1 - an selects the two data element block; a0 selects the first access within the block. 2 . for a burst length of four, a2 - an selects the four data element block; a0 - a1 selects the first access within the block. 3 . for a burst length of eight, a3 - an selects the eight data element block; a0 - a2 selects the first access within the block. 4 . for the optional burst length of sixteen, a4 - an selects the sixteen data element block; a0 - a3 selects the first access within the block. 5 . whenever a boundary of th e block is reached within a given sequence, the following access wraps within the block. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1 - an when the burst length is set to two, by a2 - an when the burst length is set to 4, by a3 - an when the burst length is set to 8 and a4 - an when t he burst length is set to 16(where an is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length appl ies to both read and write bursts. 6.4 b urst t ype accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determin ed by the burst length, the burst type and the starting column address , as shown in the previous table. 6.5 r ead l atency the read latency is the delay between the registration of a read command and the availability of the first piece of output data. the latency should be set to 2 or 3 clocks. if a read command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at n + 2 tck + tac. if a read command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid at n + tck + tac. 6.6 e xtended m ode r egister d escription the extended mode register controls functions beyond those controlled by the mode register; these additional functions include output drive strength selection and partial array self refresh (pasr). pasr is effective in self refresh mode only. the extended mode registe r is programmed via the mode register set command (with ba1=1 and ba0=0) and will retain the stored information until i t is reprogrammed, the device is put in deep power down mode, or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tmrd before initiatin g any subsequent operation. violating either of these requirements will result in unspecified operation. address bits a0 - a2 specify pasr, a5 - a 7 the driver strength. a logic 0 should be programmed to all the undefined addresses bits to ensure future compat ibility. reserved states should not be used, as unknown operation or incompatibility with future versions may result.
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 16 - revision a 01 - 00 3 6.6.1 extended mode register definition 6.7 status register read status register read (srr) is an optional feature in jedec, and it is implemented in this device. with srr, a method is defined to read registers from the device. the encoding for an srr command is the same as a mrs with ba[1:0]=01. the address pins (a[n:0]) encode which register is to be read. currently only one register is defined at a[n:0]=0. the sequence to perform an srr command is as follows: ? all reads/writes must be completed ? all banks must be closed ? mrs with ba=01 is issued (srr) ? wait tsrr ? read issued to any bank/page ? cas latency cycles later the device returns the registers data as it would a normal read ? the next command to the device can be issued tsrc after the read command was issued. the burst length for the srr read is always fixed to length 2. e x t e n d e d m o d e r e g . a d d r e s s b u s a 0 a 1 a 2 a 3 a 4 a 5 a 7 ~ a n . . . . a 8 ( 1 ) b a 0 b a 1 1 0 0 ( 2 ) d s r e s e r v e d p a s r a 6 a 5 d r i v e s t r e n g t h 0 1 1 1 1 0 0 0 f u l l s t r e n g t h d r i v e r h a l f s t r e n g t h d r i v e q u a r t e r s t r e n g t h d r i v e r a 2 a 1 a 0 p a s r 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 a l l b a n k s 1 / 2 a r r a y ( b a 1 = 0 ) 1 / 4 a r r a y ( b a 1 = b a 0 = 0 ) r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d n o t e s : 1 . m s b d e p e n d s o n m o b i l e d d r s d r a m d e n s i t y . 2 . a l o g i c 0 s h o u l d b e p r o g r a m m e d t o a l l u n u s e d / u n d e f i n e d b i t s t o e n s u r e f u t u r e c o m p a t i b i l i t y . o c t a n t s t r e n g t h d r i v e r a 7 0 0 0 1 0 0 0 t h r e e - q u a r t e r s s t r e n g t h d r i v e r
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 17 - revision a 01 - 00 3 6.7.1 srr register ( a[n:0] = 0) r i s i n g e d g e o f d q b u s s r r r e g i s t e r 0 m a n u f a c t u r e r m a n u f a c t u r e r i d e n t i f i c a t i o n r e v i s i o n i d e n t i f i c a t i o n r e f r e s h r a t e r e s e r v e d ( 0 ) d e n s i t y d t d w d q 3 d q 2 d q 1 d q 0 d e n s i t y d q 1 3 d q 1 4 d q 1 5 d q 1 2 d e v i c e t y p e r e f r e s h r a t e d q 1 0 d q 9 d q 8 0 3 4 7 8 1 0 1 1 1 2 1 3 1 5 1 6 x 0 0 0 1 w i n b o n d l p d d r r e s e r v e d 0 1 r e v i s i o n i d d e v i c e w i d t h 1 6 b i t s 3 2 b i t s 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 8 2 5 6 5 1 2 1 0 2 4 2 0 4 8 r e s e r v e d r e s e r v e d 6 4 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 x r e s e r v e d 0 . 2 5 r e s e r v e d 1 r e s e r v e d r e s e r v e d r e s e r v e d ( s e e n o t e 1 ) d q 7 : 4 d q 1 1 n o t e 2 : t h e r e f r e s h r a t e m u l i t i p l i e r i s b a s e d o n t h e m e n o r y s t e m p e r a t u r e s e n s o r . n o t e 3 : r e q u i r e d a v e r a g e p e r i o d i c r e f r e s h i n t e r v a l = t r e f i * m u l t i p l i e r n o t e 1 : t h e m a n u f a c t u r e s r e v i s i o n n u m b e r s t a r t s a t 0 0 0 0 a n d i n c r e m e n t s b y 0 0 0 1 e a c h t i m e a c h a n g e i n t h e m a n u f a c t u r e r s s p e c i f i c a t i o n ( a c t i m i n g s , o r f e a t u r e s e t ) , i b i s ( p u l l u p o r p u l l d o w n c h a r a c t e r i s t i c s ) , o r p r o c e s s o c c u r s .
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 18 - revision a 01 - 00 3 6.7.2 status register read timing diagram notes : 1. srr can only be issued after power - up sequence is complete. 2. srr can only be issued with all banks precharged. 3. srr cl is unchanged from value in the mode register. 4. srr bl is fixed at 2. 5. tsrr = 2 (min). 6. tsrc = cl + 1; (min time between read to next valid command) 7. no commands other than nop and des are allowed between the srr and the read. c m d c m d n o p n o p n o p n o p n o p m r s r e a d c l = 3 0 0 1 t r p t s r r t s r c d q : r e g o u t = d o n t c a r e p c h a , o r p c h c k c k c o m m a n d b a 1 , b a 0 a n C a 0 d q s d q
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 19 - revision a 01 - 00 3 6.8 p artial a rray s elf r efresh with partial array self refresh (pasr), the self refresh may be restricted to a variable portion of the total array. the whole array (default), 1/2 array, or 1/4 array could be selected. data outside the defined area will be lost. address bits a0 to a2 are used to set pasr. 6.9 automatic t emperature c ompensated s elf r efresh the device has an automatic temperature compensated self refresh feature . it automatically adjust s the refresh rate based on the device temperature without any register update needed. to maintain backward compatibility, this device which have automatic tcsr, ignore (don?t care) the inputs to address bits a3 and a4 during emrs programming. 6.10 o utput d rive s trength the drive strength could be set to full , half or three - quarter strength via address bits a5 and a6. the half drive strength option is intended for lighter loads or point - to - point environments. 6 . 11 c ommands all commands (address and control signals) are registered on the positive edge of clock (crossing of ck going high and going low). 6.11.1 basic timing parameters for commands ck c k c k i n p u t v a l i d v a l i d v a l i d t c l t c h t c k t i s t i h : d o n ' t c a r e n o t e : i n p u t = a 0 C a n , b a 0 , b a 1 , c k e , c s , r a s , c a s , w e ;
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 20 - revision a 01 - 00 3 6.11.2 truth table - command s name (function) ba a10 / ap addr notes deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 ac tive (select bank and activate r ow) l l h h v alid row row read (select bank and column and start read burst) l h l h v alid l col read with ap (read burst with auto p recharge) l h l h v alid h col 3 write (select bank and column and start write burst) l h l l v alid l col write with ap (write burst with auto p recharge) l h l l v alid h col 3 burst terminate or enter deep power down l h h l x x x 4, 5 precharge (deactivate row in selected bank) l l h l v alid l x 6 prechar ge all (deactivate rows in all b anks) l l h l x h x 6 auto refresh or enter self refresh l l l h x x x 7, 8, 9 mode register set l l l l v alid op - code 10 notes: 1. all states and sequences not shown are illegal or reserved. 2. deselect and nop are functionally interchangeable. 3. auto precharge i s non - persistent. a10 high enables auto precharge, while a10 low disables auto precharge. 4. burst terminate applies to only read bursts with a utoprecharge disabled. this command is undefined and should not be used for read with auto precharge enabled, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged. if a10 is high, all banks are precharged and ba0~ba1 are don?t care. 7. this command is auto refresh if cke is high and self refresh if cke is low. 8. all address inputs and i/o are ?don?t care? except for cke. int ernal refresh counters control b ank and r ow addressing. 9. all banks must be precharged before issuing an auto - refresh or self refres h command. 10. ba0 and ba1 value select between mrs and emrs. 11. cke is high for all commands shown except self refresh and deep power - down. we cas ras cs
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 21 - revision a 01 - 00 3 6.11.3 truth table - dm operations function dm dq notes write enable l valid 1 write inhibit h x 1 notes: 1. used to mask write data, provided coincident with the corresponding data. 6.11.4 truth table - cke cken - 1 cken c urrent s tate commandn actionn notes l l power down x maintain power down l l self refresh x maintain self refresh l l deep power down x maintain deep power down l h power down nop or deselect exit power down 5, 6, 9 l h self refresh nop or deselect exit self refresh 5, 7, 10 l h deep power down nop or deselect exit deep power down 5, 8 h l all banks idle nop or deselect precharge power down entry 5 h l bank(s) active nop or deselect active power down entry 5 h l all banks idle auto refresh self refresh entry h l all banks idle burst terminate enter deep power down h h see the other truth tables notes: 1. cken is the logic state of cke at clock edge n; cken - 1 was the state of cke at the previous clock edge. 2. current state is the state of lpddr immediately prior to clock edge n. 3. commandn is the command registered at clock edge n, and actionn is the result of commandn. 4. all stat es and sequences not shown are illegal or reserved. 5. deselect and nop are functionally interchangeable. 6. power down exit time (txp) should elapse before a command other than nop or deselect is issued. 7. self refresh exit time (txsr) should elapse before a comm and other than nop or deselect is issued. 8. the deep power - down exit procedure must be followed as discussed in the deep power - down section of the f unctional d escription. 9. th e clock must toggle at least on ce during the txp period. 10. the clock must toggle at lea st once during the txsr time.
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 22 - revision a 01 - 00 3 6.11.5 truth table - current state bankn - command to bankn current state command action notes any h x x x deselect nop or continue previous o peration l h h h n o operation nop or continue previous o peration idle l l h h active select and activ ate row l l l h auto refresh auto refresh 10 l l l l m rs mode register set 10 row active l h l h read select c olumn & start read burst l h l l write select c olumn & start write burst l l h l precharge deactivate r ow in bank (or banks) 4 read (auto precha r ge disabled ) l h l h read select column & start new r ead burst 5, 6 l h l l write select column & start w rite burst 5, 6, 13 l l h l precharge truncate r ead burst , start p recharge l h h l b urst t erminate burst terminate 11 write (auto precha r ge disabled ) l h l h read select column & start r ead burst 5, 6, 12 l h l l write select column & start new w rite burst 5, 6 l l h l precharge truncate write burst & start p recharge 12 notes: 1. the table applies when both cken - 1 and cken are high, and af ter txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for precharging. 5. a command other than nop should not be issued to the s ame bank while a read or write b urst with a uto p recharge is enabled. 6. the new read or write command could be a uto p rechrge enabled or a uto p recharge disabled. 7. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read bur st has been initiated, with a uto p recharge disabled, and has not yet terminated or been terminat ed . write: a w rite bur st has been initiated, with a uto p recharge disabled, and has not yet terminated or been terminated. 8. the following states must not be interrupted by a command issued to the same bank. desedect or nop commands or allowable commands to t he other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and this table , and according to next table . precharging: starts with the registration of a precharge c ommand and ends when trp is met. once trp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be in the ?row active? state. read with ap enab led: starts with the registrati on of the read command with a uto p recharge enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. write with ap enabled: starts with registrat ion of a write command with a uto p rech arge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. 9. the following states must not be interrupted by any executable command; desedect or nop commands must be applied to each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when trfc is met. once trfc is met, the lpddr will be in an ?all banks idle? state. we cas ras cs
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 23 - revision a 01 - 00 3 accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once tmrd is met, the lpddr will be in an ?all banks idle? state. p recharg ing all: st arts with the registration of a precharge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 10. not bank - specific; requires that all banks are idle and no bursts are in progress. 11. not bank - specific. burst terminate affects the most recent read burst, regardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the completion of the read burst; otherwise, a b urst terminate must be used to end the read prior to asserting a write command. 6.11.6 truth table - current state ba nkn, command to bank n current state comman d action notes any h x x x deselect nop or continue previous operation l h h h nop nop or continue previous operation idle x x x x any any command allowed to bank m row activating, active, or precharg ing l l h h active select and activate r ow l h l h read select column & s tart read burst 8 l h l l write s elect column & start write burst 8 l l h l precharge precharge read with auto precharge disabled l l h h active select and a ctivate r ow l h l h read s elect column & start new read burst 8 l h l l write s elect column & start write burst 8,10 l l h l precharge precharge write with auto precharge disabled l l h h active select and a ctiv ate r ow l h l h read s elect column & start read burst 8, 9 l h l l write s elect column & start new write burst 8 l l h l precharge precharge read with auto precharge l l h h active select and activate row l h l h read s elect column & start new read burst 5, 8 l h l l write s elect column & start write burst 5, 8, 10 l l h l precharge precharge write with auto precharge l l h h active select and a ctivate r ow l h l h read select column & start read burst 5, 8 l h l l write s elect column & start new write burst 5, 8 l l h l precharge precharge we cas ras cs
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 24 - revision a 01 - 00 3 notes: 1. the table applies when both cken - 1 and cken are high, and after txsr or txp has been met if the previous state was self r efresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. current state definitions: idle: the bank has been precharge d , and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been init iated, with a uto p recharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with a uto p recharge disabled, and has not yet terminated or been terminated. 5. read with ap enabled and write with ap enabled: the re ad with auto p recharge enabled or write with auto p recharge enabled states can be broken into two parts: the access period and the precharge period. for read with ap, the precharge period is defined as if the same burst was executed with auto precharge dis abled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr measured as if auto precharge was disabled. the access pe riod starts with registration of the command and ends where the precharge period (or trp) begins. during the precharge period, of the read with auto p recharge enabled or write with auto p recharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other banks may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided). 6. auto r efresh, self refresh, and mode register set commands may only be issued when all bank are idle. 7. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 8. reads or writes listed in the command column include reads and writes with a uto precharge enabled and reads and writes with a uto precharge disabled. 9. requires appropriate dm masking. 10. a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command. 7 . operation 7 .1 . d eselect the deselect function ( = high) prevents new commands from being executed by the lpddr sdram. the lpddr sdram is effectively deselected . operatio ns already in progress are not affected. 7 .2. n o o peration the no operation (nop) command is used to perform a nop to a lpddr sdram that is selected ( =low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. cs
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 25 - revision a 01 - 00 3 7.2.1 nop command 7 .3 m ode r egister s et the mode register and the extended mode register are loaded via the address inputs. the mode register set command can only be i ssued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tmrd is met. 7.3.1 m ode r egister s et command = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n b a 0 , b a 1 = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n b a 0 , b a 1 c o d e c o d e
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 26 - revision a 01 - 00 3 7.3.2 mode register set command timing 7 .4. a ctive before any read or write commands can be issued to a bank in the lpddr sdram, a row in that bank must be opened. this is accomplished by the active command: ba0 and ba1 select the bank, and the address inputs select the row to be activated. more than one bank can be active at any time. once a row is open, a read or write command could be issued to that row, subject to the t rcd specification. a subsequent active command to another row in the same bank can only b e issued after the previous row has been closed. the minimum time interval between two successive active commands on the same bank is defined by t rc . 7.4.1 a ctive command c k c k c o m m a n d m r s : d o n ' t c a r e n o t e : c o d e = m o d e r e g i s t e r / e x t e n d e d m o d e r e g i s t e r s e l e c t i o n ( b a 0 , b a 1 ) a n d o p - c o d e ( a 0 - a n ) c o d e v a l i d v a l i d n o p t m r d a d d r e s s = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n b a 0 , b a 1 r a b a b a = b a n k a d d r e s s , r a = r o w a d d r e s s
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 27 - revision a 01 - 00 3 a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row - access overhead. the minimum time interval between two successive active commands on different banks is defined by t rrd . the row remains active until a precharge comm and (or read or write command with auto precharge) is issued to the bank. a precharge (or read with a uto precharge or write with a uto precharge ) command must be issued before opening a different row in the same bank. 7.4.2 bank activation command cycle 7 .5. r ead the read command is used to initiate a burst read access to an active row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the starting column location. the value of a10 determines whether or not auto pre - charge is used. if auto pre - charge is selected, the row being accessed will be pre - charged at the end of the read burst; if auto pre - charge is not selected, the row will rem ain open for subsequent accesses. n o p n o p n o p a c t a c t n o p r d / w r r o w r o w c o l b a x b a y b a y t r c d t r r d = d o n ' t c a r e c k c k c o m m a n d a 0 - a n b a 0 , b a 1
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 28 - revision a 01 - 00 3 7.5.1 r ead command the basic read timing parameters for dqs are shown in following figure ; they apply to all read operations. 7.5.2 basic r ead timing parameters = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n c a a p b a = b a n k a d d r e s s c a = c o u l m n a d d r e s s a p = a u t o p r e c h a r g e b a b a 0 , b a 1 a 1 0 e n a b l e a p d i s a b l e a p c k c k t d q s q m a x t a c t l z t q h t q h t h z d o n + 3 d o n + 2 d o n + 1 d o n t r p r e t r p s t t d q s c k t d q s c k t d q s q m a x t a c t l z t q h t q h t h z d o n + 3 d o n + 2 d o n + 1 d o n t r p r e t r p s t t d q s c k t d q s c k = d o n , t c a r e 1 ) d o n = d a t a o u t f r o m c o l u m n n 2 ) a l l d q a r e v a i l d t a c a f t e r t h e c k e d g e . a l l d q a r e v a l i d t d q s q a f t e r t h e d q s e d g e , r e g a r d l e s s o f t a c d q s d q d q s d q t c k t a c m a x t a c m i n t c k t c h t c l
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 29 - revision a 01 - 00 3 during read bursts, dqs is driven by the lpddr sdram along with the output data. the initial low state of the dqs is known as the read preamble; the low state coincident with last data - out element is known as the read post - amble. the first data - out eleme nt is edge aligned with the first rising edge of dqs and the successive data - out elements are edge aligned to successive edges of dqs. this is shown in following figure with a cas latency of 2 and 3. upon completion of a read burst, assuming no other read command has been initiated, the dqs will go to high - z. 7.5.3 read burst showing cas latency 7.5.4 r ead to r ead data from a read burst may be concatenated or truncated by a subsequent read co mmand. the first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data - out element pairs (pairs are required by the 2n - prefetch architect ure). this is shown in following f igure . c l = 2 d o n d o n = d o n ' t c a r e b a c o l n r e a d n o p n o p n o p n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d q s d q 1 ) d o n = d a t a o u t f r o m c o l u m n n 2 ) b a , c o l n = b a n k a , c o l u m n n 3 ) b u r s t l e n g t h = 4 ; 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n 4 ) s h o w n w i t h n o m i n a l t a c , t d q s c k a n d t d q s q c l = 3
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 30 - revision a 01 - 00 3 7.5. 5 consecutive read bursts 7.5. 6 non - c onsecutive read bursts a read command can be initiated on any clock cycle following a previous read command. non - consecutive reads are shown in following figure. c l = 2 d o n d o n = d o n ' t c a r e b a , c o l n r e a d n o p r e a d n o p n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d q s d q 1 ) d o n ( o r b ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n b ) 2 ) b u r s t l e n g t h = 4 , 8 o r 1 6 ( i f 4 , t h e b u r s t s a r e c o n c a t e n a t e d ; i f 8 o r 1 6 , t h e s e c o n d b u r s t i n t e r r u p t s t h e f i r s t ) 3 ) r e a d b u r s t s a r e t o a n a c t i v e r o w i n t h e b a n k 4 ) s h o w n w i t h n o m i n a l t a c , t d q s c k a n d t d q s q b a , c o l b c l = 3 d o b d o b c l = 2 d o n d o n = d o n ' t c a r e b a , c o l n r e a d n o p n o p r e a d n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d q s d q 1 ) d o n ( o r b ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n b ) 2 ) b a , c o l n ( b ) = b a n k a , c o l u m n n ( b ) 3 ) b u r s t l e n g t h = 4 ; 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n ( b ) 4 ) s h o w n w i t h n o m i n a l t a c , t d q s c k a n d t d q s q d o b c l = 3 b a , c o l b
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 31 - revision a 01 - 00 3 7.5. 7 random read bursts full - speed random read accesses within a page or pages can be performed as shown in following f igure. 7.5. 8 r ead b urst t erminate data from any read burst may be truncated with a burst termin ate command, as shown in figure. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command where x equals the desired data - out element pairs. c l = 2 d o n d o n = d o n ' t c a r e b a , c o l n r e a d r e a d n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d q s d q 1 ) d o n , e t c . = d a t a o u t f r o m c o l u m n n , e t c . n i , x i , e t c . = d a t a o u t e l e m e n t s , a c c o r d i n g t o t h e p r o g r a m m e d b u r s t o r d e r 2 ) b a , c o l n = b a n k a , c o l u m n n 3 ) b u r s t l e n g t h = 2 , 4 , 8 o r 1 6 i n c a s e s s h o w n ( i f b u r s t o f 4 , 8 o r 1 6 , t h e b u r s t i s i n t e r r u p t e d ) 4 ) r e a d s a r e t o a c t i v e r o w s i n a n y b a n k s b a , c o l b c l = 3 b a , c o l x r e a d r e a d b a , c o l g d o n i d o x i d o x d o b d o g d o b i d o g i d o b i d o b d o x i d o x d o n i c l = 2 = d o n ' t c a r e b a , c o l n r e a d n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d q s d q 1 ) d o n = d a t a o u t f r o m c o l u m n n 2 ) b a , c o l n = b a n k a , c o l u m n n 3 ) c a s e s s h o w n a r e b u r s t s o f 4 , 8 o r 1 6 t e r m i n a t e d a f t e r 2 d a t a e l e m e n t s . 4 ) s h o w n w i t h n o m i n a l t a c , t d q s c k a n d t d q s q c l = 3 b s t n o p n o p
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 32 - revision a 01 - 00 3 7.5. 9 r ead to w rite data from read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in following figure for the case of nominal tdqss 7.5. 10 r ead to pre - charge a read burst may be followed by or truncated with a precharge command to the same bank (provided auto pre - charge was not activated). the precharge command should be issued x cycles after the read command, where x equal the number of desired data - out element pairs. this is shown in following figure. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row pre - charge time is hidden during the access of the last data - out elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result fro m read burst with auto pre - charge enabled. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. c l = 2 b a , c o l n r e a d n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d m 1 ) d o n = d a t a o u t f r o m c o l u m n n ; d i b = d a t a i n t o c o l u m n b 2 ) b u r s t l e n g t h = 4 , 8 o r 1 6 i n t h e c a s e s s h o w n ; i f t h e b u r s t l e n g t h i s 2 , t h e b s t c o m m a n d c a n b e o m i t t e d 3 ) s h o w n w i t h n o m i n a l t a c , t d q s c k a n d t d q s q b s t w r i t e n o p = d o n ' t c a r e b a , c o l n r e a d w r i t e n o p b s t n o p n o p b a , c o l b b a , c o l b t d q s s d o n c l = 3 d q s d q d m d o n c o m m a n d a d d r e s s
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 33 - revision a 01 - 00 3 7.5.1 1 b urst t erminate of r ead the burst terminate command is used to truncate read bursts (with auto pre - charge disabled). the most recently registered read command prior to the burst terminate command will be truncated. note that the burst terminate command is not bank specific. this command should not be used to terminate write bursts. 7 .6 w rite the write command is used to initiate a burst write access to an active row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the starting column location. the value of a10 determines whether or not auto pre - charge is used. if auto pre - charge is selected, the row being accessed will be pre - charged at the end of the write burst; if auto pre - charge is not selected, the row will remain open for subseq uent accesses. 1 ) d o n = d a t a o u t f r o m c o l u m n n 2 ) c a s e s s h o w n a r e e i t h e r u n i n t e r r u p t e d o f 4 , o r i n t e r r u p t e d b u r s t s o f 8 o r 1 6 3 ) s h o w n w i t h n o m i n a l t a c , t d q s c k a n d t d q s q 4 ) p r e c h a r g e m a y b e a p p l i e d a t ( b l / 2 ) t c k a f t e r t h e r e a d c o m m a n d . 5 ) n o t e t h a t p r e c h a r g e m a y n o t b e i s s u e d b e f o r e t r a s n s a f t e r t h e a c t i v e c o m m a n d f o r a p p l i c a b l e b a n k s . 6 ) t h e a c t i v e c o m m a n d m a y b e a p p l i e d i f t r c h a s b e e n m e t . c l = 2 d o n d o n = d o n ' t c a r e b a , c o l n r e a d n o p p r e n o p n o p n o p c k c k c o m m a n d a d d r e s s d q s d q d q s d q c l = 3 b a n k ( a o r a l l ) b a , r o w t r p ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n b a 0 , b a 1 = d o n ' t c a r e
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 34 - revision a 01 - 00 3 7.6.1 w rite command 7.6.2 basic write timing parameters basic write timing parameters for dqs are shown in figure below ; they apply to all write operations. input data appearing on the data bus, is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n c a a p b a = b a n k a d d r e s s c a = c o u l m n a d d r e s s a p = a u t o p r e c h a r g e b a b a 0 , b a 1 a 1 0 e n a b l e a p d i s a b l e a p d i n d i n t c k t c h t c l t d s h t d s h t d q s h t d q s s t w p r e s t w p r e t d s t d h t d q s l t w p s t c k c k d q s d q s d q , d m c a s e 1 : t d q s s = m i n c a s e 2 : t d q s s = m a x t d h t d s t w p r e s t w p r e t d q s h t d q s s t d s s t d q s l t d s s t w p s t = d o n ' t c a r e 1 ) d i n = d a t a i n f o r c o l u m n n 2 ) 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n . 3 ) t d q s s : e a c h r i s i n g e d g e o f d q s m u s t f a l l w i t h i n t h e + / - 2 5 % w i n d o w o f t h e c o r r e s p o n d i n g p o s i t i v e c l o c k e d g e . d q , d m
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 35 - revision a 01 - 00 3 7.6.3 write burst (min. and max. tdqss) during write bursts, the first valid data - in element will be registered on the first rising edge of dqs fol lowing the write command, and the subsequent data elements will be registered on successive edges of dqs. the low state of dqs between the write command and the first rising edge is called the write preamble, and the low state on dqs following the last dat a - in element is called the write post - amble. the time between the write command and the first corresponding rising edge of dqs (t dqss ) is specified with a relatively wide range - from 75% to 125% of a clock cycle. following figure shows the two extremes of t dqss for a burst of 4 , u pon completion of a burst, assuming no other commands have been initiated, the dqs will remain high - z and any additional input data will be ignored. 7.6.4 w rite to w rite data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data, can be maintained. the new write command can be issued on any positive edge of the clock following the previous write command. the first dat a - in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data - in element pairs. b a , c o l b w r i t e n o p n o p c k c k c o m m a n d a d d r e s s 1 ) d i b = d a t a i n t o c o l u m n b . 2 ) 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i b . 3 ) a n o n - i n t e r r u p t e d b u r s t o f 4 i s s h o w n . 4 ) a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) n o p n o p n o p = d o n ' t c a r e d q s d q d m d q s d q d m t d q s s m i n t d q s s m a x
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 36 - revision a 01 - 00 3 7.6.5 concatenated write bursts a n example of con catenated write bursts is shown in figure below . 7.6.6 non - consecutive write bursts a n example of non - consecutive write bursts is shown in figure below . b a , c o l b w r i t e n o p n o p c k c k c o m m a n d a d d r e s s 1 ) d i b ( n ) = d a t a i n t o c o l u m n b ( c o l u m n n ) 2 ) 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i b . 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n . 3 ) n o n - i n t e r r u p t e d b u r s t s o f 4 a r e s h o w n . 4 ) e a c h w r i t e c o m m a n d m a y b e t o a n y a c t i v e b a n k n o p n o p w r i t e = d o n ' t c a r e d q s d q d m d q s d q d m t d q s s m i n b a , c o l n t d q s s m a x d i b d i b d i n d i n b a , c o l n b a , c o l b w r i t e n o p n o p c k c k c o m m a n d a d d r e s s 1 ) d l b ( n ) = d a t a i n t o c o l u m n b ( o r c o l u m n n ) 2 ) 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i b . 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n . 3 ) n o n - i n t e r r u p t e d b u r s t s o f 4 a r e s h o w n . 4 ) e a c h w r i t e c o m m a n d m a y b e t o a n y a c t i v e b a n k a n d m a y b e t o t h e s a m e o r d i f f e r e n t d e v i c e s . n o p n o p w r i t e = d o n ' t c a r e d q s d q d m t d q s s m a x b a , c o l n
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 37 - revision a 01 - 00 3 7.6.7 random write cycles full - speed random write accesses within a page or pages can be performed as shown in figure below . 7.6.8 w rite to r ead data for any write burst may be followed by a subsequent read command. 7.6.9 non - interrupting write to read to follow a write without truncating the write burst, t wtr should be met as shown in the figure below . b a , c o l n b a , c o l b w r i t e w r i t e n o p c k c k c o m m a n d a d d r e s s 1 ) d l b e t c . = d a t a i n t o c o l u m n b , e t c . ; b , e t c . = t h e n e x t d a t a i n f o l l o w i n g d l b , e t c . a c c o r d i n g t o t h e p r o g r a m m e d b u r s t o r d e r 2 ) p r o g r a m m e d b u r s t l e n g t h = 2 , 4 , 8 o r 1 6 i n c a s e s s h o w n . i f b u r s t o f 4 , 8 o r 1 6 , b u r s t w o u l d b e t r u n c a t e d 3 ) e a c h w r i t e c o m m a n d m a y b e t o a n y a c t i v e b a n k a n d m a y b e t o t h e s a m e o r d i f f e r e n t d e v i c e s . w r i t e w r i t e w r i t e = d o n ' t c a r e d q s d q d m t d q s s m a x b a , c o l a b a , c o l x b a , c o l n b a , c o l g d i b d i b d i x d i x d i n d i n d i a d i a b a , c o l b w r i t e n o p n o p c k c k c o m m a n d a d d r e s s 1 ) d l b = d a t a i n t o c o l u m n b 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i b . 2 ) a n o n - i n t e r r u p t e d b u r s t o f 4 i s s h o w n . 3 ) t w t r i s r e f e r e n c e d f r o m t h e p o s i t i v e c l o c k e d g e a f t e r t h e l a s t d a t a i n p a i r . 4 ) a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) 5 ) t h e r e a d a n d w r i t e c o m m a n d s a r e t o t h e s a m e d e v i c e b u t n o t n e c e s s a r i l y t o t h e s a m e b a n k . n o p n o p r e a d = d o n ' t c a r e d q s d q d m t d q s s m a x b a , c o l n t w t r c l = 3 d i b n o p
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 38 - revision a 01 - 00 3 7.6.10 interr upting write to read data for any write burst may be truncated by a subsequent read command as shown in the figure below . note that the only data - in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent da ta - in must be masked with dm. 7.6.11 w rite to p recharge data for any write burst may be followed by a subsequent precharge command to the same bank (provided auto precharge was not activated). to follow a write without truncating the write burst, t wr should be met as shown in the f igure below . 7.6.12 non - interrupting write to precharge b a , c o l n b a , c o l b w r i t e n o p n o p c k c k c o m m a n d a d d r e s s 1 ) d l b = d a t a i n t o c o l u m n b . d o n = d a t a o u t f r o m c o l u m n n . 2 ) a n i n t e r r u p t e d b u r s t o f 4 i s s h o w n , 2 d a t a e l e m e n t s a r e w r i t t e n . 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i b . 3 ) t w t r i s r e f e r e n c e d f r o m t h e p o s i t i v e c l o c k e d g e a f t e r t h e l a s t d a t a i n p a i r . 4 ) a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) 5 ) t h e r e a d a n d w r i t e c o m m a n d s a r e t o t h e s a m e d e v i c e b u t n o t n e c e s s a r i l y t o t h e s a m e b a n k . n o p n o p r e a d = d o n ' t c a r e d q s d q d m t d q s s m a x b a , c o l n t w t r c l = 3 d i b d o n n o p b a , c o l n b a , c o l b w r i t e n o p p r e c k c k c o m m a n d a d d r e s s 1 ) d l b = d a t a i n t o c o l u m n b 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i b . 2 ) a n o n - i n t e r r u p t e d b u r s t o f 4 i s s h o w n . 3 ) t w r i s r e f e r e n c e d f r o m t h e p o s i t i v e c l o c k e d g e a f t e r t h e l a s t d a t a i n p a i r . 4 ) a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) n o p n o p n o p = d o n ' t c a r e d q s d q d m t d q s s m a x b a a ( o r a l l ) t w r d i b
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 39 - revision a 01 - 00 3 7.6.13 interrupting write to precharge data for any write burst may be truncated by a subsequent prechar ge command as shown in figure below . note that only data - in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data - in should be masked with dm, as shown in figure. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. 7 .7 p recharge the precharge command is used to deactivate the open row in a particular bank or the open row in all ban ks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged. in case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as don?t care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write command being issued. a precharge command will be treated as a nop if there is no op en row in that bank, or if the previously open row is already in the process of precharging. b a , c o l n b a a ( o r a l l ) b a , c o l b w r i t e p r e n o p c k c k c o m m a n d a d d r e s s 1 ) d l b = d a t a i n t o c o l u m n b . 2 ) a n i n t e r r u p t e d b u r s t o f 4 , 8 o r 1 6 i s s h o w n , 2 d a t a e l e m e n t s a r e w r i t t e n . 3 ) t w r i s r e f e r e n c e d f r o m t h e p o s i t i v e c l o c k e d g e a f t e r t h e l a s t d e s i r e d d a t a i n p a i r . 4 ) a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) 5 ) * 1 = c a n b e d o n ' t c a r e f o r p r o g r a m m e d b u r s t l e n g t h o f 4 6 ) * 2 = f o r p r o g r a m m e d b u r s t l e n g t h o f 4 , d q s b e c o m e s d o n ' t c a r e a t t h i s p o i n t n o p n o p n o p = d o n ' t c a r e d q s d q d m t d q s s m a x t w r d i b * 1 * 1 * 1 * 1 * 2
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 40 - revision a 01 - 00 3 7.7.1 p recharge command 7 .8 a uto p recharge auto precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. this is accomplished by using a10 (a10 = high), to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank / row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is non persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharing time (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this specification . 7 .9 r efresh r equ irements lpddr sdram devices require a refresh of all rows in any rolling 64ms interval. each refresh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode. dividing the number of device rows into the rolling 64ms interval defines the average refresh interval (t refi ), which is a guideline to controllers for distributed refresh timing. 7 . 10 a uto r efresh auto refresh command is used during normal operation of the lpddr sdram. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. the lpddr sdram requires auto refresh commands at an average periodic interval of t refi. = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a d d r e s s b a = b a n k a d d r e s s ( i f a 1 0 = l , o t h e r w i s e d o n ' t c a r e ) b a b a 0 , b a 1 a 1 0 a l l b a n k s o n e b a n k
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 41 - revision a 01 - 00 3 7.10.1 a uto r efresh command 7.11 s elf r eferesh the sel f refresh command can be used to retain data in the lpddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the lpddr sdram retains data without external clocking. the lpddr sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is initiated like an auto refresh command except cke is low. input signals except cke are don?t care during self refresh. the user may halt the external clock one clock after the self refresh command is registered. once the command is registered, cke must be held low to keep the device in self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the device must remain in self refresh mode is t rfc . the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self refr esh exit is registered, a delay of at least t xs must be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally tim ed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. in the self refresh mode, one additional power - saving option exist: partial array self refresh (pa sr); it is described in the extended mode register section . = d o n ' t c a r e ( h i g h ) c k c k c k e c s r a s c a s w e a 0 - a n b a 0 , b a 1
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 42 - revision a 01 - 00 3 7.1 1.1 s elf r efresh command 7.1 1.2 auto refresh cycles back - to - back = d o n ' t c a r e c k c k c k e c s r a s c a s w e a 0 - a n b a 0 , b a 1 p r e n o p a r f n o p n o p n o p a r f n o p a c t b a , a r o w n r o w n p r e a l l h i g h - z c k c k c o m m a n d a d d r e s s a 1 0 ( a p ) d q t r p t r f c t r f c = d o n ' t c a r e b a a , r o w n = b a n k a , r o w n
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 43 - revision a 01 - 00 3 7.1 1.3 self refresh entry and exit 7.12 power down power - down is entered when cke is registered low (no accesses can be in progress). if power - down occurs when all banks are idle, this mode is referred to as precharge power - dow n; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down. entering power - down deactivates the input and output buffers, excluding ck, and cke. in power - down mode, cke low must be m aintained, and all other input signals are don?t care. the minimum power - down duration is specified by t cke . however, power - down duration is limited by the refresh requirements of the device. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid command may be applied t xp after exit from power - down. for clock stop during power - down mode, please refer to the clock stop subsection in this specification. 7.12.1 power - down entry and exit ck p r e n o p a r f n o p a r f n o p p r e a l l h i g h - z c k c k c o m m a n d a 1 0 ( a p ) d q t r p > t r f c t r f c = d o n ' t c a r e a d d r e s s n o p t x s r a n y c o m m a n d ( a u t o r e f r e s h r e c o m m e n e d ) e x i t f r o m s e l f r e f r e s h m o d e e n t e r s e l f r e f r e s h m o d e c k e a c t n o p b a , a r o w n r o w n p r e n o p n o p n o p n o p v a l i d p r e a l l h i g h - z c k c k c o m m a n d a 1 0 ( a p ) d q t r p t c k e t x p a d d r e s s n o p a n y c o m m a n d e x i t f r o m p o w e r d o w n p o w e r d o w n e n t r y v a l i d v a l i d p r e c h a r g e p o w e r - d o w n m o d e s h o w n ; a l l b a n k s a r e i d l e a n d t r p i s m e t w h e n p o w e r - d o w n e n t r y c o m m a n d i s i s s u e d = d o n ' t c a r e c k e
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 44 - revision a 01 - 00 3 7.13 d eep p ower d own the deep power - down (dpd) mode enables very low standby currents. all internal voltage generators inside the lpddr sdram are stopped and all memory data is lost in this mode. all the information in t he mode register and the extended mode register is lost. deep power - down is entered using the burst terminate command except that cke is registered low. all banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this state, cke must be held in a constant low state. to exit the dpd mode, cke is taken high after the clock is stable and nop commands must be maintained for at least 200 s. after 200 s a complete re - initialization is required following steps 4 throu gh 11 as defined for the initialization sequence . 7.13.1 deep power - down entry and exit t r p t = 2 0 0 u s e x i t d p d m o d e e n t e r d p d m o d e = d o n ' t c a r e 1 ) c l o c k m u s t b e s t a b l e b e f o r e e x i t i n g d e e p p o w e r - d o w n m o d e . t h a t i s , t h e c l o c k m u s t b e c y c l i n g w i t h i n s p e c i f i c a t i o n s b y t a 0 2 ) d e v i c e m u s t b e i n t h e a l l b a n k s i d l e s t a t e p r i o r t o e n t e r i n g d e e p p o w e r - d o w n m o d e 3 ) 2 0 0 u s i s r e q u i r e d b e f o r e a n y c o m m a n d c a n b e a p p l i e d u p o n e x i t i n g d e e p - d o w n m o d e 4 ) u p o n e x i t i n g d e e p p o w e r - d o w n m o d e a p r e c h a r g e a l l c o m m a n d m u s t b e i s s u e d , f o l l o w e d b y t w o r e f r e s h c o m m a n d s a n d a l o a d m o d e r e g i s t e r s e q u e n c e n o p d p d n o p v a l i d v a l i d t a 2 t a 1 t a 0 t 0 t 1 c k c k c k e c o m m a n d a d d r e s s d q s d q d m
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 45 - revision a 01 - 00 3 7.14 c lock s top stopping a clock during idle periods is an effective method of reducing power consumption. the lpddr sdram supports clock stop under the following conditions: ? the last command (active, read, write, precharge, auto refresh or mode register set) has executed to completion, including any data - out during read bursts; the number of clock pulses per access command depends on the device?s ac timing parameters and the clock frequency; ? the related timing conditions (t rcd , t wr , t rp , t rfc , t mrd ) has been met; ? cke is held high when all conditions have been met, the device is either in idle stat e or row active state and clock stop mode may be entered with ck held low and held high. clock stop mode is exited by restarting the clock. at least one nop command has to be issued before the next access command may be applied. a dditional clock pulses might be required depending on the system characteristics. the following figure shows clock stop mode entry and exit. ? initially the device is in clock stop mode ? the clock is restarted with the rising edge of t0 and a nop on the comm and inputs ? with t1 a valid access command is latched; this command is followed by nop commands in order to allow for clock stop as soon as this access command is completed ? tn is the last clock pulse required by the access command latched with t1 ? the clock can be stopped after tn 7.14.1 clock stop mode entry and exit ck v a l i d n o p c m d n o p n o p n o p t n t 2 t 1 t 0 c k c k c k e c o m m a n d d q , d q s t i m i n g c o n d i t i o n ( h i g h - z ) = d o n ' t c a r e e n t e r c l o c k s t o p m o d e v a l i d c o m m a n d e x i t c l o c k s t o p m o d e c l o c k s t o p p e d a d d r e s s
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 46 - revision a 01 - 00 3 8. elec t r ical characteristic 8.1 a bsolute m aximum r atings parameter symbol values units min max voltage on vdd relative to vss vdd ? 0.3 2.7 v voltage on vddq relative to vss vddq ? 0.3 2.7 v voltage on any pin relative to vss vin, vout ? 0.3 2.7 v operating case temperature t c ? 25 - 40 85 85 c storage temperature tstg ? 55 150 c short circuit output current iout 50 ma power dissipation pd 1.0 w 8 .2 i nput /o utput c apacitance [notes 1 - 3] parameter symbol min max units notes input capacitance, ck, cck 1.5 3. 0 pf input capacitance delta, ck, cdck 0.25 pf input capacitance, all other input - only pins ci 1.5 3 .0 pf input capacitance delta, all other input - only pins cdi 0 .5 pf input/ output capacitance, dq,dm,dqs cio 3 .0 5.0 pf 4 input/output capacitance delta, dq, dm, dqs cdio 0.50 pf 4 notes: 1. these values are guaranteed by design and are tested on a sample base only. 2. these capacitance values are for single monolithic devices only. multiple die packages will have parallel capacitive loads. 3. although dm is an input - only pin, the input capacitance of this pin must model the input capacitance of the dq and dqs pi ns. this is required to match signal propagation times of dq, dqs and dm in the system. ck
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 47 - revision a 01 - 00 3 8 .3 e lectrical c haracteristics and ac/dc o perating c onditions all values are recommended operating conditions unless otherwise noted. 8.3.1 electrical characteristics a nd ac/dc operating conditions parameter/condition symbol min max units notes supply voltage vdd 1.7 0 1.9 5 v i/o supply voltage vddq 1.7 0 1.9 5 v address and command inputs (a0~an, ba0,ba1,cke, , , , ) input high voltage vih 0.8*vddq vddq + 0.3 v input low voltage vil ? clock inputs (ck, ) dc input voltage vin ? data inputs (dq, dm, dqs) dc input high voltage vihd (dc) 0.7*vddq vddq + 0.3 v dc input low voltage vild (dc) ? ? data outputs (dq, dqs) dc output high voltage (ioh=?0.1ma) leakage current input leakage current iil - 1 1 ua output leakage current iol - 5 5 ua notes: 1. all voltages referenced to vss and vssq must be same potential. 2. vid (dc) and vid (ac) are the magnitude of the difference between the input level on ck and . 3. the value of vix is expected to be 0.5*vddq and must track variations in the dc level of the same. ck we cas ras cs
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 48 - revision a 01 - 00 3 8 .4 idd s pecification p arameters and t est c onditions 8.4.1 idd specification parameters a nd test conditions [recommended operating conditions; notes 1 - 3] ( 128 mb, x16) parameter symbol test condition - 5 - 6 - 75 unit operating one bank active - precharge current idd0 trc = trcmin ; tck = tckmin ; cke is high; is high between valid commands; address inputs are switching; data bus inputs are stable 40 38 35 ma precharge power - down standby current idd2p all banks idle, cke is low; is high, tck = tckmin ; address and control inputs are switching; data bus inputs are stable low power 0.23 0.23 0.23 ma normal power 0.28 0.28 0.28 precharge power - down standby current with clock stop idd2ps all banks idle, cke is low; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable low power 0.23 0.23 0.23 ma normal power 0.28 0.28 0.28 precharge non power - down standby current idd2n all banks idle, cke is high; is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 10 10 10 ma precharge non power - down standby current with clock stop idd2ns all banks idle, cke is high; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable 3 3 3 ma active power - down standby current idd3p one bank active, cke is low; is high, tck = tckmin;address and control inputs are switching; data bus inputs are stable 3 3 3 ma active power - down standby current with clock stop idd3ps one bank active, cke is low; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable 3 3 3 ma active non power - down standby current idd3n one bank active, cke is high; is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 25 20 20 ma active non power - down standby current with clock stop idd3ns one bank active, cke is high; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable 15 12 12 ma operating burst read current idd4r one bank active; bl = 4; cl = 3; tck = tckmin ; continuous read bursts; iout = 0 ma; address inputs are switching; 50% data change each burst transfer 75 70 70 ma operating burst write current idd4w one bank active; bl = 4; t ck = t ckmin ; continuous write bursts; address inputs are switching; 50% data change each burst transfer 55 50 50 ma auto - refresh current idd5 trc = trfcmin ; tck = tckmin ; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 50 50 50 ma deep power - down current idd8 (4) address and control inputs are stable; data bus inputs are stable 10 10 10 ua cs ck
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 49 - revision a 01 - 00 3 ( 128 mb, x32) parameter symbol test condition - 5 - 6 - 75 unit operating one bank active - precharge current idd0 trc = trcmin ; tck = tckmin ; cke is high; is high between valid commands; address inputs are switching; data bus inputs are stable 40 38 35 ma precharge power - down standby current idd2p all banks idle, cke is low; is high, tck = tckmin ; address and control inputs are switching; data bus inputs are stable low power 0.23 0.23 0.23 ma normal power 0.28 0.28 0.28 precharge power - down standby current with clock stop idd2ps all banks idle, cke is low; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable low power 0.23 0.23 0.23 ma normal power 0.28 0.28 0.28 precharge non power - down standby current idd2n all banks idle, cke is high; is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 10 10 10 ma precharge non power - down standby current with clock stop idd2ns all banks idle, cke is high; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable 3 3 3 ma active power - down standby current idd3p one bank active, cke is low; is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 3 3 3 ma active power - down standby current with clock stop idd3ps one bank active, cke is low; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable 3 3 3 ma active non power - down standby current idd3n one bank active, cke is high; is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 25 20 20 ma active non power - down standby current with clock stop idd3ns one bank active, cke is high; is high, ck = low, = high; address and control inputs are switching; data bus inputs are stable 15 12 12 ma operating burst read current idd4r one bank active; bl = 4; cl = 3; tck = tckmin ; continuous read bursts; iout = 0 ma; address inputs are switching; 50% data change each burst transfer 75 70 70 ma operating burst write current idd4w one bank active; bl = 4; t ck = t ckmin ; continuous write bursts; address inputs are switching; 50% data change each burst transfer 55 50 50 ma auto - refresh current idd5 trc = trfcmin ; tck = tckmin ; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 50 50 50 ma deep power - down current idd8(4) address and control inputs are stable; data bus inputs are stable 10 10 10 ua notes: 1. idd specifications are tested after the device is properly initialized. 2. input slew rate is 1v/ns. 3. definitions for idd: low is defined as v in 0.1 * v ddq ;high is defined as v in 0.9 * v ddq ; stable is defined as inputs stable at a high or low level; switching is defined as: - address and command: inputs changing between high and low once per two clock cycles; - data bus inputs: dq changing between high and low once per clock cycle; dm and dqs are stable. 4. idd8 are typical value at 25 . cs ck
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 50 - revision a 01 - 00 3 idd6 conditions : i dd 6 low power normal power units a tcsr range 45 85 45 85 ua full array 180 230 220 280 1/2 array 160 200 190 250 1/4 array 150 180 170 230 n otes : 1. measured with outputs open. 2 . idd6 is typical value . .
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 51 - revision a 01 - 00 3 8 .5 ac t imings [recommended operating conditions: notes 1 - 9] parameter symbol - 5 - 6 - 7 5 unit notes min max min max min max dq output access time from ck/ cl=3 tac 2.0 5.0 2.0 5.0 2.0 6.0 ns cl=2 2.0 6.5 2.0 6.5 2.0 6.5 dqs output access time from ck/ cl=3 tdqsck 2.0 5.0 2.0 5.0 2.0 6.0 ns cl=2 2.0 6.5 2.0 6.5 2.0 6.5 clock high - level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low - level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck clock half period thp min (tcl, tch) min (tcl, tch) min (tcl, tch) ns 10,11 clock cycle time cl=3 tck 5 6 7.5 ns 12 cl=2 12 12 12 ns 12 dq and dm input setup time fast tds 0.48 0.6 0.8 ns 13,14,15 slow 0.58 0.7 0.9 ns 13,14,16 dq and dm input hold time fast tdh 0.48 0.6 0.8 ns 13,14,15 slow 0.58 0.7 0.9 ns 13,14,16 dq and dm input pulse width tdipw 1.6 1.6 1.8 ns 17 address and control input setup time fast tis 0.9 1.1 1.3 ns 15,18 slow 1.1 1.3 1.5 ns 16,18 address and control input hold time fast tih 0.9 1.1 1.3 ns 15,18 slow 1.1 1.3 1.5 ns 16,18 address and control input pulse width tipw 2.3 2.6 2.6 ns 17 dq & dqs low - impedance time from ck/ tlz 1.0 1.0 1.0 ns 19 dq & dqs high - impedance time from ck/ cl=3 thz 5.0 5.0 6.0 ns 19 cl=2 6.5 6.5 6.5 dqs - dq skew tdqsq 0.4 0.5 0.6 ns 20 dq/dqs output hold time from dqs tqh thp - tqhs thp - tqhs thp - tqhs ns 11 data hold skew factor tqhs 0.5 0 . 65 0.75 ns 11 write command to 1st dqs latching transition tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs input high - level width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs input low - level width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 0.2 0.2 tck dqs falling edge hold time from ck tdsh 0.2 0.2 0.2 tck mode register set command tmrd 2 2 2 tck ck
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 52 - revision a 01 - 00 3 parameter symbol - 5 - 6 - 7 5 unit notes min max min max min max period write preamble setup time twpres 0 0 0 ns 21 write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 22 write preamble twpre 0.25 0.25 0.25 tck read preamble cl = 3 trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck 23 cl = 2 0.5 1.1 0.5 1.1 0.5 1.1 tck 23 read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck active to precharge command period tras 40 70,000 42 70,000 45 70,000 ns active to active command period trc tras+ trp tras+ trp tras+ trp ns auto refresh to active/auto refresh command period trfc 72 72 72 ns active to read or write delay trcd 15 18 22.5 ns precharge command period trp 3 3 3 tck active bank a to active bank b delay trrd 10 12 15 ns write recovery time twr 15 15 15 ns 24 auto precharge write recovery + precharge time tdal - - - tck 2 5 internal write to read command delay twtr 2 2 1 tck self refresh exit to next valid command delay txsr 120 120 120 ns 2 6 exit power down to next valid command delay txp 2 1 1 tck 2 7 cke min. pulse width (high and low pulse width) tcke 1 1 1 tck refresh period tref 64 64 64 ms average periodic refresh interval trefi 15.6 15.6 15.6 s 28 mrs for srr to read tsrr 2 2 2 tck read of srr to next valid command tsrc cl+1 cl+1 cl+1 tck
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 53 - revision a 01 - 00 3 note s : 1. all voltages referenced to vss. 2. all parameters assume proper device initialization. 3. tests for ac timing may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage and temperature range specified. 4. the circuit shown below represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). for the half strength driver with a nominal 1 0pf load parameters tac and tqh are expected to be in the same range. however, these parameters are not subject to production test but are estimated by design / characterization. use of ibis or other simulation tools for system design validation is suggest ed. 5. the ck/ input reference voltage level (for timing referenced to ck/ ) is the point at which ck and cross; the input reference voltage level for signals other than ck/ is vddq/2. 6. the timing reference voltage level is vddq/2. 7. ac and dc input and output voltage levels are defined in the section for electrical characteristics and ac/d c operating conditions. 8. a ck/ differential slew rate of 2.0 v/ns is assumed for all parameters. 9. latency definition: with cl = 3 the first data element is valid at (2 * tck + tac) after the clock at which the re a d command was registered ; with cl = 2 the first data element is valid at (tck + tac) after the clock at which the read command was registered 10. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to th e device (i.e. this value can be greater than the minimum specification limits of tcl and tch) 11. tqh = thp - tqhs, where thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tcl, tch). tqhs accounts for 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p - ch annel to n - channel variation of the output drivers. 12. the only time that the clock frequency is allowed to change is during clock stop, power - down or self - refresh modes. 13. the transition time for dq, dm and dqs inputs is measured between vil(dc) to vih(ac) for rising input signals, and vih(dc) to vil(ac) for falling input signals. 14. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. 15. input sle w rate 1.0 v/ns. 16. input slew rate 0.5 v/ns and < 1.0 v/ns. 17. these parameters guarantee device timing but they are not necessarily tested on each device. 18. the transition time for address and command inputs is measured between vih and vil. t i m e r e f e r e n c e l o a d i / o z 0 = 5 0 o h m s 2 0 p f ck cas
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 54 - revision a 01 - 00 3 19. thz and tlz trans itions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 20. tdqsq consists of data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers for any given cycle. 21. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before the corresponding ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi - z to logic low. if a previous write was in progress, dqs could be high, low, or tran sitioning from high to low at this time, depending on tdqss. 22. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 23. a low le vel on dqs may be maintained during high - z states (dqs drivers disabled) by adding a weak pull - down element in the system. it is recommended to turn off the weak pull - down element during read and write bursts (dqs drivers enabled). 24. at least one clock cycle is required during twr time when in auto precharge mode. 25. tdal = (twr/tck) + (trp/tck): for each of the terms, if not already an integer, round to the next higher integer. 26. there must be at least two clock pulses during the txsr period. 27. there must be at le ast one clock pulse during the txp period. 28. a maximum of 8 refresh commands can be posted to any given lpddr sdram , meaning that the maximum absolute interval between any refresh command and the next refresh command is 8*trefi. 8.5.1 cas latency definition (with cl=3) c l = 3 t l z m i n t r p r e t d q s c k m i n t d q s c k m i n t r p s t t 5 n t 5 t 4 n t 3 n t 2 n t 4 t 3 t 2 r e a d n o p n o p n o p n o p n o p n o p c o m m a n d c k c k d q s a l l d q , c o l l e c t i v e l y 1 ) d q t r a n s i t i o n i n g a f t e r d q s t r a n s i t i o n d e f i n e t d q s q w i n d o w . 2 ) a l l d q m u s t t r a n s i t i o n b y t d q s q a f t e r d q s t r a n s i t i o n s , r e g a r d l e s s o f t a c 3 ) t a c i s t h e d q o u t p u t w i n d o w r e l a t i v e t o c k , a n d i s t h e l o n g t e r m c o m p o n e n t o f d q s k e w . t 0 t 1 t 2 t 2 n t 3 t 3 n t 4 t 4 n t 5 t 5 n t 6 t l z m i n
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 55 - revision a 01 - 00 3 8.5.2 output slew rate characteristics parameter min max unit notes pull - up and pull - down slew rate for full strength driver 0.7 2.5 v/ns 1,2 pull - up and pull - down slew rate for three - quarter strength driver 0.5 1.75 v/ns 1,2 pull - up and pull - down slew rate for half strength driver 0.3 1.0 v/ns 1,2 output slew rate matching ratio (pull - up to pull - down) 0.7 1.4 - 3 notes: 1. measured with a test load of 20 pf connected to v ssq . 2. output slew rate for rising edge is measured between vild(dc) to vihd(ac) and for falling edge between vihd(dc) to vild(ac). 3. the ratio of pull - up slew rate to pull - down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pull - up and pull - down drivers due to process variation. 8.5.3 ac overshoot/undershoot specification parameter specification maximum peak amplitude allowed for overshoot 0.5 v maximum peak amplitude allowed for undershoot 0.5 v the area between overshoot signal and vdd must be less than or equal to 3 v - ns the area between undershoot signal and gnd must be less than or equal to 3 v - ns 8.5.4 ac overshoot and undershoot definition v d d v s s 2 . 5 2 . 0 1 . 5 1 . 0 0 . 5 0 - 0 . 5 o v e r s h o o t a r e a u n d e r s h o o t a r e a m a x a m p l i t u d e = 0 . 5 v m a x a r e a = 3 v - n s v o l t a g e ( v ) t i m e ( n s )
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 56 - revision a 01 - 00 3 9 . package d imensions 9 .1 : lpddr x 16 vbga60 b all ( 8x9 mm^2, ball pitch:0.8mm) n o t e : 1 . b a l l l a n d : 0 . 5 m m . b a l l o p e n i n g : 0 . 4 m m . p c b b a l l l a n d s u g g e s t e d Q 0 . 4 m m 2 . d i m e n s i o n s a p p l y t o s o l d e r b a l l s p o s t - r e f l o w . t h e p r e - r e f l o w d i a m e t e r i s 0 . 4 2 o n a 0 . 4 s m d b a l l p a d .
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 57 - revision a 01 - 00 3 9 .2: lpddr x 32 vbga90 b all ( 8x13 mm^2, ball pitch:0.8mm) n o t e : 1 . b a l l l a n d : 0 . 5 m m . b a l l o p e n i n g : 0 . 4 m m . p c b b a l l l a n d s u g g e s t e d Q 0 . 4 m m 2 . d i m e n s i o n s a p p l y t o s o l d e r b a l l s p o s t - r e f l o w . t h e p r e - r e f l o w d i a m e t e r i s 0 . 4 2 o n a 0 . 4 s m d b a l l p a d .
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 58 - revision a 01 - 00 3 10. o rdering information w 9 4 7 d 6 h b h x 5 i mobile lpddr/lpsdr sdram package part numbering product line 98:mobile lpsdr sdram 94:mobile lpddr sdram density 7:2 7 =128m 8:2 8 =256m 9:2 9 =512m power supply d:1.8/1.8 v dd / v ddq i/o ports width 6:16bit 2:32bit temperature with standard idd6 g: - 25c~85c package material x: lead - free + halogen - free package or kgd k: kgd b: bga package configuration code g: 54vfbga, 8mmx9mm h: 60vfbga, 8mmx9mm j: 90vfbga, 8mmx13mm generation design revision. with low power idd6 e: - 25c~85c i: - 40c~85c clock rate 5:5ns ? ? ? part number v dd /v ddq i/o width package others w947d6hbhx5i 1.8v/1.8v 16 60vfbga 200mhz, -40c~85c, low power w947d6hbhx5e 1.8v/1.8v 16 60vfbga 200mhz, -25c~85c, low power w947d6hbhx6e 1.8v/1.8v 16 60vfbga 166mhz, -25c~85c, low power w947d6hbhx6g 1.8v/1.8v 16 60vfbga 166mhz, -25c~85c W947D2HBJX5I 1.8v/1.8v 32 90vfbga 200mhz, -40c~85c, low power w947d2hbjx5e 1.8v/1.8v 32 90vfbga 200mhz, -25c~85c, low power w947d2hbjx6e 1.8v/1.8v 32 90vfbga 166mhz, -25c~85c, low power w947d2hbjx6g 1.8v/1.8v 32 90vfbga 166mhz, -25c~85c
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 59 - revision a 01 - 00 3 11. revision history version date page description a01 - 001 04 / 08 / 2011 all product datasheet for customer . a01 - 002 04 / 18 / 2011 17 52 delete 2 in refresh rate of srr for dq8~10.
w 94 7 d6 hb / w 94 7 d2 hb 128 m b m obile lpddr publication release date: jun , 17 , 2011 - 60 - revision a 01 - 00 3 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wher e in personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. ----------------------------------------------------------------------------------------------------------------------------- -------------------- please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in the datasheet belong to their respective owners

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